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Old 05-26-2008, 08:08 PM
bigfoot bigfoot is offline
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Default Is it a bad Inverter board?

Is it a bad Inverter board?

Q: I have a HP Pavilion zd7000 laptop, it do not feel the heat. But the bottom of the screen is among the logo of “HP” where a high temperature, a bit of scalding hot has. Some people say that the board is bad; the called “inverter” board is so hot. For you to ask, if the inverter board is bad it will be very hot?
One month ago, I have used it about 6 hours probably, machine is very hot, I ‘m shutdown my laptop, and waiting the temperature drop-down by a cool Fan. After 5 minutes later, Boot up my laptop was on a blank screen. Held several times it will not work.
One hour later, the rest will be open to all normal. Now, the screen has been replaced. But inverter still is hot and has a some problem. This is my laptop the case; please help me how to be fixed!

A: Please replace a good inverter board to your laptop, also unplug the LCD Flex cable and then plug it back. Thanks.

 

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Old 06-02-2008, 04:12 PM
Cristinalee Cristinalee is offline
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Default GS880Z18AT-225I pdf and datasheet

GS880Z18AT-225I pdf
Functional Description
The GS880Z18/36AT is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
The GS880Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of
clock. The GS880Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDEC-Standard 100-pin TQFP package.

Last edited by bigfoot : 06-21-2009 at 05:05 PM.
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Old 09-04-2010, 08:28 AM
Gigawatt Gigawatt is offline
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Thank you very much for the information..............
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